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Allwinner /D1H /SMHC[0] /SMHC_IDST

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Interpret as SMHC_IDST

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TX_INT)TX_INT 0 (RX_INT)RX_INT 0 (FATAL_BERR_INT)FATAL_BERR_INT 0 (DES_UNAVL_INT)DES_UNAVL_INT 0 (ERR_FLAG_SUM)ERR_FLAG_SUM 0 (NOR_INT_SUM)NOR_INT_SUM 0 (ABN_INT_SUM)ABN_INT_SUM 0IDMAC_ERR_STA

Description

IDMAC Status Register

Fields

TX_INT

Transmit Interrupt
RX_INT

Receive Interrupt
FATAL_BERR_INT

Fatal Bus Error Interrupt
DES_UNAVL_INT

Descriptor Unavailable Interrupt
ERR_FLAG_SUM

Card Error Summary
NOR_INT_SUM

Normal Interrupt Summary
ABN_INT_SUM

Abnormal Interrupt Summary
IDMAC_ERR_STA

Error Bits

1 (transmission): Host Abort received during the transmission

2 (reception): Host Abort received during the reception

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data